I. Field of the Invention
The present invention relates to the field of conservation of power in electronic circuits. More specifically, the present invention relates to circuits with reduced leakage currents.
II. Background Information
With the advent of deep sub-micron Complementary Metal Oxide Semiconductor (CMOS) processes, the sub-threshold current leakage current I.sub.off seen in a turned-off transistor has increased dramatically from that of earlier CMOS processes. The finer the sub-micron features are--i.e., smaller line widths and process features, the more pronounced the increase in a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) drain's leakage current I.sub.off, This high I.sub.off has led to very high cumulative currents, (I.sub.off(chip)) arising in very large scale integrated (VLSI) circuits that are in an Idle or inactive state. An idle state is defined as a state in which no switching activity occurs and in which no DC bias currents is present.
The leakage current (I.sub.off(chip)) has risen to a point where new generation products of integrated circuit (IC) families may not meet the I.sub.off(chip) current specifications that where achievable in earlier processes. In earlier processes, it was possible to achieve I.sub.off(chip) currents in the 10s to 100s of microamperes for a microprocessor having approximately 2 million transistors, for example. For higher performance microprocessors fabricated by way of low feature sub-micron processes, I.sub.off(chip) may be in a range of approximately 10-100 milliamperes for ICs that feature finer geometry. This higher leakage current is between 100 to 1,000 times the leakage current of earlier sub-micron devices and causes a great problem for IC parts, such as microprocessors, for example, used in applications requiring ultra-low standby power.
FIG. 1 depicts a drain-to-source current (I.sub.ds) as a function of gate-to-source voltage (V.sub.gs) for a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Ideally, when V.sub.gs of the MOSFET is below the threshold voltage (V.sub.t), i.e., V.sub.gs -V.sub.t &lt;0, Ids equals 0. In reality, I.sub.ds is not equal to 0 for gate voltages that are lower than V.sub.t as one may see from graph 102 representing Log I.sub.ds as a function of V.sub.gs. When V.sub.gs, equals 0 volts, a leakage current I.sub.off1 flows through the transistor.
In many instances, such as in the case of mobile devices that are powered by batteries, the process features are scaled down and the power supply levels are collapsed to lower and lower voltages, so that the batteries may last longer. As the process scales down and the supply voltages are reduced to lower voltages, drain-to-source voltages (V.sub.ds) are pushed down. In these cases, for lower supply voltages V.sub.dd, V.sub.t is also lowered to make the process faster. Also, for finer processes such as sub-micron CMOS geometry processes, V.sub.dd is decreased to keep electrical or electromagnetic fields from punching through the transistor's channel region. If V.sub.t was not lowered, a relatively large voltage would need to be applied to the gate of a MOSFET to turn that transistor on. This would cause a degradation in the performance of the electronic circuit to the sub-optimal MOSFET characteristic. As V.sub.t is lowered, the leakage current increases to I.sub.off2 as one may see from graph 104. The leakage current I.sub.off2, for the state where V.sub.t is lowered, depicted by graph 104, is higher than the leakage current I.sub.off1 for the state depicted by graph 102. As I.sub.off goes up, the power consumed by the electronic circuit incorporating the MOSFET also goes up. It is desirable to reduce power consumption for fine feature CMOS processes such as sub-micron CMOS processes.